This technical seminar focuses on cutting-edge developments in AI chip design, EDA automation, HPC, and advanced semiconductor technologies. We sincerely invite distinguished speakers from both academia and industry to share in-depth insights.
The event is designed to go beyond pure technical discussion, offering conversations that combine industrial perspective with commercial insights.
The conference features two core highlights:
This seminar will feature a lineup of internationally recognized speakers, including IEEE award recipients, international patent holders, and industry technology leaders who also serve as adjunct professors at top universities.
The speakers span both academic research and industrial practice, with deep expertise in AI processor architecture, chip design automation, and next-generation semiconductor processes. They will deliver insights that combine theoretical depth with real-world application experience.
The forum brings together technology leaders from both academia and industry to discuss:
How AI design tools are reshaping IC development workflows
Deployment strategies for HPC infrastructure
Opportunities and risks for the semiconductor supply chain under the rise of AI
Participants will exchange first-hand, practical perspectives on these critical topics.
※ Topics are subject to change depending on speaker availability.
Semiconductor industry professionals
Engineers and managers who want to understand how AI is transforming semiconductor R&D cycles and assess whether their current technical strategy aligns with industry shifts.
Low-power HPC system developers
System architects and hardware engineers addressing the trade-offs between high performance computing and power efficiency, seeking actionable insights from real-world implementations.
EDA tool users and IC design teams
Engineers and technical leaders evaluating AI-driven EDA tools and exploring how they can be integrated into existing design workflows to improve efficiency.
Edge AI chip designers and application developers
Hardware designers working on or selecting edge inference chips who need to understand architecture trends and power optimization methodologies.
Advanced packaging R&D engineers
Professionals focused on chiplet architecture and heterogeneous integration who are interested in how AI can optimize packaging design and testing workflows.
This forum welcomes participants from across the semiconductor value chain and provides opportunities for cross-disciplinary exchange and collaboration.